The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2013
Filed:
Nov. 30, 2011
Jan Gray, Bellevue, WA (US);
Martin Taillefer, Redmond, WA (US);
Yossi Levanoni, Redmond, WA (US);
Ali-reza Adl-tabatabai, San Jose, CA (US);
Dave Detlefs, Issaquah, WA (US);
Vinod Grover, Mercer Island, WA (US);
Mike Magruder, Sammamish, WA (US);
Matt Tolton, Kirkland, WA (US);
Bratin Saha, Santa Clara, CA (US);
Gad Sheaffer, Haifa, IL;
Vadim Bassin, Rannnana, IL;
Jan Gray, Bellevue, WA (US);
Martin Taillefer, Redmond, WA (US);
Yossi Levanoni, Redmond, WA (US);
Ali-Reza Adl-Tabatabai, San Jose, CA (US);
Dave Detlefs, Issaquah, WA (US);
Vinod Grover, Mercer Island, WA (US);
Mike Magruder, Sammamish, WA (US);
Matt Tolton, Kirkland, WA (US);
Bratin Saha, Santa Clara, CA (US);
Gad Sheaffer, Haifa, IL;
Vadim Bassin, Rannnana, IL;
Intel Corporation, Santa Clara, CA (US);
Abstract
In one embodiment, the present invention includes a method for selecting a first transaction execution mode to begin a first transaction in a unbounded transactional memory (UTM) system having a plurality of transaction execution modes. These transaction execution modes include hardware modes to execute within a cache memory of a processor, a hardware assisted mode to execute using transactional hardware of the processor and a software buffer, and a software transactional memory (STM) mode to execute without the transactional hardware. The first transaction execution mode can be selected to be a highest performant of the hardware modes if no pending transaction is executing in the STM mode, otherwise a lower performant mode can be selected. Other embodiments are described and claimed.