Memory module having signal lines configured for sequential arrival of signals at a plurality of memory devices

Abstract

A memory module includes a substrate, a plurality of signal lines, a clock line and a plurality of memory devices. The plurality of signal lines including first and second signal lines routed alongside one another where, for each of the first and second signal lines, a respective signal, starting at a corresponding first edge finger, traverses in sequence, a respective first segment of a respective signal line, a respective turn portion of the respective signal line, and a respective second segment of the respective signal line. The clock line is to provide a clock signal that traverses in sequence, a second edge finger, the first segment of the clock line, the turn portion of the clock line, and the second segment of the clock line. The respective signals traverse and the clock signal line arrive at the plurality of memory devices in sequence.