The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2013
Filed:
Jun. 08, 2010
Hsiao-tsung Yen, Tainan, TW;
Hsien-pin HU, Zhubei, TW;
Jhe-ching LU, Tainan, TW;
Chin-wei Kuo, Zhubei, TW;
Ming-fa Chen, Taichung, TW;
Sally Liu, HsinChu, TW;
Hsiao-Tsung Yen, Tainan, TW;
Hsien-Pin Hu, Zhubei, TW;
Jhe-Ching Lu, Tainan, TW;
Chin-Wei Kuo, Zhubei, TW;
Ming-Fa Chen, Taichung, TW;
Sally Liu, HsinChu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV.