The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2013
Filed:
Jan. 19, 2010
Jin-bum Kim, Seoul, KR;
Wook-je Kim, Gwacheon-si, KR;
Kwan-heum Lee, Suwon-si, KR;
Yu-gyun Shin, Seongnam-si, KR;
Sun-ghil Lee, Yongin-si, KR;
Jin-bum Kim, Seoul, KR;
Wook-je Kim, Gwacheon-si, KR;
Kwan-heum Lee, Suwon-si, KR;
Yu-gyun Shin, Seongnam-si, KR;
Sun-ghil Lee, Yongin-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
A method of manufacturing a semiconductor device may include forming a first interlayer insulation layer on a substrate including at least one gate structure formed thereon, the substrate having a plurality of source/drain regions formed on both sides of the at least one gate structure, forming at least one buried contact plug on at least one of the plurality of source/drain regions and in the first interlayer insulation layer, forming a second interlayer insulation layer on the first interlayer insulation layer and the at least one buried contact plug, exposing the at least one buried contact plug in the second interlayer insulation layer by forming at least one contact hole, implanting ions in the at least one contact hole in order to create an amorphous upper portion of the at least one buried contact plug, depositing a lower electrode layer on the second interlayer insulation layer and the at least one contact hole, and forming a metal silicide layer in the amorphous upper portion of the at least one buried contact plug.