The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2013

Filed:

Jan. 19, 2011
Applicants:

Jeffrey B. Johnson, Essex Junction, VT (US);

Ramachandran Muralidhar, Mahopac, NY (US);

Philip J. Oldiges, Lagrangeville, NY (US);

Viorel C. Ontalus, Danbury, CT (US);

Kai Xiu, Pleasantville, NY (US);

Inventors:

Jeffrey B. Johnson, Essex Junction, VT (US);

Ramachandran Muralidhar, Mahopac, NY (US);

Philip J. Oldiges, Lagrangeville, NY (US);

Viorel C. Ontalus, Danbury, CT (US);

Kai Xiu, Pleasantville, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers.


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