The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 01, 2013
Filed:
Mar. 30, 2010
Vishnu K. Khemka, Phoenix, AZ (US);
Tahir A. Khan, Tempe, AZ (US);
Weixiao Huang, Tempe, AZ (US);
Ronghua Zhu, Chandler, AZ (US);
Vishnu K. Khemka, Phoenix, AZ (US);
Tahir A. Khan, Tempe, AZ (US);
Weixiao Huang, Tempe, AZ (US);
Ronghua Zhu, Chandler, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
Transistors () employing floating buried layers may be susceptible to noise coupling into the floating buried layers. In IGFETS this is reduced or eliminated by providing a normally-ON switch () coupling the buried layer () and the IGFET source () or drain (). When the transistor () is OFF, this clamps the buried layer voltage and substantially prevents noise coupling thereto. When the drain-source voltage Vexceeds the switch's () threshold voltage Vt, it turns OFF, allowing the buried layer () to float, and thereby resume normal transistor action without degrading the breakdown voltage or ON-resistance. In a preferred embodiment, a normally-ON lateral JFET (---) conveniently provides this switching function. The lateral JFET (-) can be included in the device () by mask changes without adding or customizing any process steps, thereby providing the improved noise resistance without significant increase in manufacturing cost. The improvement applies to both P (-) and N channel (---) transistors and is particularly useful for LDMOS devices.