The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2012
Filed:
Oct. 04, 2010
Robert D. Herzl, South Burlington, VT (US);
Robert S. Horton, Colchester, VT (US);
Kenneth A. Lauricella, Colchester, VT (US);
David W. Milton, Underhill, VT (US);
Clarence R. Ogilvie, Huntington, VT (US);
Paul M. Schanely, Essex Junction, VT (US);
Nitin Sharma, South Burlington, VT (US);
Tad J. Wilder, South Hero, VT (US);
Charles B. Winn, Colchester, VT (US);
Robert D. Herzl, South Burlington, VT (US);
Robert S. Horton, Colchester, VT (US);
Kenneth A. Lauricella, Colchester, VT (US);
David W. Milton, Underhill, VT (US);
Clarence R. Ogilvie, Huntington, VT (US);
Paul M. Schanely, Essex Junction, VT (US);
Nitin Sharma, South Burlington, VT (US);
Tad J. Wilder, South Hero, VT (US);
Charles B. Winn, Colchester, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of forming and electrical structure. The method includes determining that a first semiconductor device requires an engineering change order (ECO). An additional structure layer required to implement the ECO is determined. A first insertion point location for inserting the additional structure layer within the first semiconductor device is selected. The first insertion point location is associated with a second insertion point location within a design for a second semiconductor device. The second semiconductor device is generated in accordance with the first ECO. The second semiconductor device comprises second structures. The second structures comprise same structures as first structures in the first semiconductor device. The second structures are formed in locations within the second semiconductor device that are associated with locations in the first semiconductor device comprising the first structures. The second semiconductor device comprises the additional structure layer located within the second insertion point location.