Dual bit line precharge architecture and method for low power dynamic random access memory (dram) integrated circuit devices and devices incorporating embedded dram

Abstract

A dual bit line precharge architecture and method for low power DRAM which provides the low operating voltage of a non-half supply voltage (VCC/2) precharge with the low memory array current consumption and low memory array noise spike of VCC/2 precharge techniques. The architecture and technique of the present invention provides both reference voltage (VSS) precharged sub arrays and VCC precharged sub arrays on the same DRAM memory either with or without the novel charge sharing or charge recycling circuitry between these two different sub arrays as disclosed herein.