The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2012

Filed:

Mar. 31, 2011
Applicants:

Jung-tzu Hsu, Taoyuan, TW;

Ching-chung Pai, Taipei, TW;

Yu-hsien Lin, Hsinchu, TW;

Jyh-huei Chen, Hsinchu, TW;

Inventors:

Jung-Tzu Hsu, Taoyuan, TW;

Ching-Chung Pai, Taipei, TW;

Yu-Hsien Lin, Hsinchu, TW;

Jyh-Huei Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/338 (2006.01);
U.S. Cl.
CPC ...
Abstract

The disclosure provides methods and structures for preventing exposing polysilicon layer and silicon substrate on the substrate backside to polysilicon etching chemistry during removal of the dummy polysilicon layer in replacement gate structures. A thermal deposition process or processes are used to deposit a dielectric layer for offset spacers and/or a contact etch stop layer (CESL) to cover the polysilicon layer on the substrate backside. Such mechanisms reduce or eliminate particles originated at bevel of substrate backside, due to complete removal of the polysilicon layer at the backside bevel and the resultant etching of silicon substrate.


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