The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 18, 2012
Filed:
Aug. 25, 2009
Kiyotaro Itagaki, Yokohama, JP;
Yoshihisa Iwata, Yokohama, JP;
Hiroyasu Tanaka, Minato-ku, JP;
Masaru Kidoh, Komae, JP;
Ryota Katsumata, Yokohama, JP;
Masaru Kito, Yokohama, JP;
Hideaki Aochi, Kawasaki, JP;
Akihiro Nitayama, Yokohama, JP;
Kiyotaro Itagaki, Yokohama, JP;
Yoshihisa Iwata, Yokohama, JP;
Hiroyasu Tanaka, Minato-ku, JP;
Masaru Kidoh, Komae, JP;
Ryota Katsumata, Yokohama, JP;
Masaru Kito, Yokohama, JP;
Hideaki Aochi, Kawasaki, JP;
Akihiro Nitayama, Yokohama, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
Each of the memory blocks includes: a first conductive layer expanding in parallel to the substrate over the first area, n layers of the first conductive layers being formed in a lamination direction and shared by the plurality of memory strings; a first semiconductor layer; and an electric charge accumulation layer. The memory strings are arranged with m columns in a second direction for each of the memory blocks. The wiring layers are arranged in the second direction, formed to extend to the vicinity of one end of the first conductive layer in the first direction from one side of the memory block, and connected via contact plugs to the first conductive layers. A relation represented by (Formula 1) is satisfied: (Formula 1) m>=n