The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 27, 2012

Filed:

May. 06, 2005
Applicants:

Armand Ferro, Phoenix, AZ (US);

Ivo Raaijmakers, Phoenix, AZ (US);

Derrick Foster, Scottsdale, AZ (US);

Inventors:

Armand Ferro, Phoenix, AZ (US);

Ivo Raaijmakers, Phoenix, AZ (US);

Derrick Foster, Scottsdale, AZ (US);

Assignee:

ASM America, Inc., Phoenix, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C23C 16/52 (2006.01); C23C 16/455 (2006.01); C23F 1/00 (2006.01); H01L 21/306 (2006.01); C23C 16/06 (2006.01); C23C 16/22 (2006.01);
U.S. Cl.
CPC ...
Abstract

A single-wafer, chemical vapor deposition reactor is provided with hydrogen and silicon source gas suitable for epitaxial silicon deposition, as well as a safe mixture of oxygen in a non-reactive gas. Methods are provided for forming oxide and silicon layers within the same chamber. In particular, a sacrificial oxidation is performed, followed by a hydrogen bake to sublime the oxide and leave a clean substrate. Epitaxial deposition can follow in situ. A protective oxide can also be formed over the epitaxial layer within the same chamber, preventing contamination of the critical epitaxial layer. Alternatively, the oxide layer can serve as the gate dielectric, and a polysilicon gate layer can be formed in situ over the oxide.


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