The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2012

Filed:

Nov. 02, 2006
Applicants:

Yunshan Zhu, Cupertino, CA (US);

James Herbert Kukula, Hillsboro, OR (US);

Robert F. Damiano, Lake Oswego, OR (US);

Joseph T. Buck, Campbell, CA (US);

Inventors:

Yunshan Zhu, Cupertino, CA (US);

James Herbert Kukula, Hillsboro, OR (US);

Robert F. Damiano, Lake Oswego, OR (US);

Joseph T. Buck, Campbell, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for digital circuit design. The first step of the process is the step of providing a circuit design in the form of a hardware definition language. Then, the process produces a binary simulation of the design by setting out for each unit of time during execution of the hardware design the a control state and a program state of the design and assigns a symbol to each signal of the design. The process proceeds by executing a symbolic simulation of the design, concluding with identifying and capturing the combinational logic expression of the simulation output and the next state functions of the simulation.


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