The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2012
Filed:
Jul. 13, 2010
Derek C. Tao, Fremont, CA (US);
Kuoyuan (Peter) Hsu, San Jose, CA (US);
Dong Sik Jeong, Fremont, CA (US);
Young Suk Kim, Fremont, CA (US);
Young Seog Kim, Pleasanton, CA (US);
Yukit Tang, Sunnyvale, CA (US);
Derek C. Tao, Fremont, CA (US);
Kuoyuan (Peter) Hsu, San Jose, CA (US);
Dong Sik Jeong, Fremont, CA (US);
Young Suk Kim, Fremont, CA (US);
Young Seog Kim, Pleasanton, CA (US);
Yukit Tang, Sunnyvale, CA (US);
Abstract
A memory array comprises a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns includes a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, and a plurality of internal supply nodes electrically coupled together and configured to receive the first voltage or the second voltage for a plurality of memory cells in the column and a plurality of internal ground nodes. The internal ground nodes are electrically coupled together and configured to provide at least two current paths for the plurality of memory cells in the column.