The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8304907 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 06, 2012

Filed:

Dec. 12, 2007
Applicants:

Mou-shiung Lin, Hsinchu, TW;

Chiu-ming Chou, Kao-Hsiung, TW;

Chien-kang Chou, Shin-Hwa Town, TW;

Inventors:

Mou-Shiung Lin, Hsinchu, TW;

Chiu-Ming Chou, Kao-Hsiung, TW;

Chien-Kang Chou, Shin-Hwa Town, TW;

Assignee:

Megica Corporation, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.


Find Patent Forward Citations

Lin, Mou-Shiung. (2012). Top layers of metal for integrated circuits (U.S. Patent No. 8304907). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8304907

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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