The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 30, 2012

Filed:

Aug. 11, 2010
Applicants:

Hsin Chang Lin, Hsinchu County, TW;

Chia-hao Tai, Hsinchu County, TW;

Yang-sen Yen, Hsinchu County, TW;

Ming-tsang Yang, Hsinchu County, TW;

Ya-ting Fan, Hsinchu County, TW;

Inventors:

Hsin Chang Lin, Hsinchu County, TW;

Chia-Hao Tai, Hsinchu County, TW;

Yang-Sen Yen, Hsinchu County, TW;

Ming-Tsang Yang, Hsinchu County, TW;

Ya-Ting Fan, Hsinchu County, TW;

Assignee:

Yield Microelectronics Corp., Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A cost saving EEPROM array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines contain a first group bit lines; the word line includes a first and a second word lines; and the common source line includes a first common source line. And, a plurality of sub-memory arrays are provided. Each sub-memory array includes a first and a second memory cells disposed opposite to each other and located on two different sides of the first common source line; the first memory cell is connected to the first group bit lines, the first common source line, and the first word line, and the second memory cell is connected to the first group bit line, the first common source line, and the second word line.


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