The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2012
Filed:
Dec. 12, 2011
Herbert L. Ho, New Windsor, NY (US);
Naoyoshi Kusaba, Hopewell Junction, NY (US);
Karen A. Nummy, Newburgh, NY (US);
Carl J. Radens, Lagrangeville, NY (US);
Ravi M. Todi, Poughkeepsie, NY (US);
Geng Wang, Stormville, NY (US);
Herbert L. Ho, New Windsor, NY (US);
Naoyoshi Kusaba, Hopewell Junction, NY (US);
Karen A. Nummy, Newburgh, NY (US);
Carl J. Radens, Lagrangeville, NY (US);
Ravi M. Todi, Poughkeepsie, NY (US);
Geng Wang, Stormville, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.