The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 23, 2012
Filed:
Aug. 12, 2009
Hoon-joo NA, Gyeonggi-do, KR;
Yu-gyun Shin, Gyeonggi-do, KR;
Hong-bae Park, Seoul, KR;
Hag-ju Cho, Gyeonggi-do, KR;
Sug-hun Hong, Gyeonggi-do, KR;
Sang-jin Hyun, Gyeonggi-do, KR;
Hyung-seok Hong, Seoul, KR;
Hoon-joo Na, Gyeonggi-do, KR;
Yu-gyun Shin, Gyeonggi-do, KR;
Hong-bae Park, Seoul, KR;
Hag-ju Cho, Gyeonggi-do, KR;
Sug-hun Hong, Gyeonggi-do, KR;
Sang-jin Hyun, Gyeonggi-do, KR;
Hyung-seok Hong, Seoul, KR;
Abstract
A semiconductor device that has a dual gate having different work functions is simply formed by using a selective nitridation. A gate insulating layer is formed on a semiconductor substrate including a first region and a second region, on which devices having different threshold voltages are to be formed. A diffusion inhibiting material is selectively injected into the gate insulating layer in one of the first region and the second region. A diffusion layer is formed on the gate insulating layer. A work function controlling material is directly diffused from the diffusion layer to the gate insulating layer using a heat treatment, wherein the gate insulting layer is self-aligned capped with the selectively injected diffusion inhibiting material so that the work function controlling material is diffused into the other of the first region and the second region. The gate insulating layer is entirely exposed by removing the diffusion layer. A gate electrode layer is formed on the exposed gate insulating layer. A first gate and a second gate having different work functions are respectively formed in the first region and the second region by etching the gate electrode layer and the gate insulating layer.