The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 23, 2012
Filed:
Nov. 13, 2009
Jun-gyeong Lee, Daejeon, KR;
Jung-youl Lee, Anyang-Si, KR;
Jeong-sik Kim, Hwaseong-Si, KR;
Eu-jean Jang, Hwaseong-Si, KR;
Jae-woo Lee, Bucheon-Si, KR;
Deog-bae Kim, Seoul, KR;
Jae-hyun Kim, Seoul, KR;
Jun-Gyeong Lee, Daejeon, KR;
Jung-Youl Lee, Anyang-Si, KR;
Jeong-Sik Kim, Hwaseong-Si, KR;
Eu-Jean Jang, Hwaseong-Si, KR;
Jae-Woo Lee, Bucheon-Si, KR;
Deog-Bae Kim, Seoul, KR;
Jae-Hyun Kim, Seoul, KR;
Dongjin Semichem .Co., Ltd., , KR;
Abstract
Disclosed is a method for manufacturing fine patterns of semiconductor devices using a double exposure patterning process for manufacturing the second photoresist patterns by simply exposing without an exposure mask. The method comprises the steps of: forming a first photoresist pattern on a semiconductor substrate on which a layer to be etched is formed; coating a composition for a mirror interlayer on the first photoresist pattern to form a mirror interlayer; forming a photoresist layer on the resultant; and forming a second photoresist pattern which is made by a scattered reflection of the mirror-interlayer and positioned between the first photoresist patterns, by exposing the photoresist layer to a light having energy which is lower than a threshold energy (E) of the photoresist layer without an exposure mask, and then developing the same.