The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2012

Filed:

Apr. 29, 2011
Applicants:

Eisaku Watanabe, Komae, JP;

Tetsuro Ogata, Chofu, JP;

Franck Ernult, Chofu, JP;

Inventors:

Eisaku Watanabe, Komae, JP;

Tetsuro Ogata, Chofu, JP;

Franck Ernult, Chofu, JP;

Assignee:

Canon Anelva Corporation, Kawasaki-shi, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a method for manufacturing a semiconductor memory element including a chalcogenide material layer and an electrode layer, each having an improved adhesion, and a sputtering apparatus thereof. One embodiment of the present invention is the method for manufacturing a semiconductor memory element including: a first step of forming the chalcogenide material layer (); and a second step of forming a second electrode layer () on the chalcogenide material layer () by sputtering through the use of a mixed gas of a reactive gas and an inert gas, while applying a cathode voltage to a target. In the second step, introduction of the reactive gas is carried out at a flow rate ratio included in a hysteresis area () appearing in the relationship between a cathode voltage applied to the cathode and the flow rate ratio of the reactive gas in the mixed gas.


Find Patent Forward Citations

Loading…