The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2012

Filed:

May. 28, 2009
Applicants:

Jae-hyoung Koo, Gyeonggi-do, KR;

Jin-woong Kim, Gyeonggi-do, KR;

Mi-ri Lee, Gyeonggi-do, KR;

Chi-ho Kim, Gyeonggi-do, KR;

Jin-ho Bin, Gyeonggi-do, KR;

Inventors:

Jae-Hyoung Koo, Gyeonggi-do, KR;

Jin-Woong Kim, Gyeonggi-do, KR;

Mi-Ri Lee, Gyeonggi-do, KR;

Chi-Ho Kim, Gyeonggi-do, KR;

Jin-Ho Bin, Gyeonggi-do, KR;

Assignee:

Hynix Semiconductor Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for forming a device isolation layer of a semiconductor device or a non-volatile memory device is provided. A method for forming a device isolation layer of a semiconductor device includes: forming trenches having a first predetermined depth by etching a substrate; forming a first insulation layer having a second predetermined depth inside the trenches; forming a liner oxide layer having a predetermined thickness on internal walls of the trenches with the first insulation layer formed therein; and forming a second insulation layer for forming a device isolation layer over the substrate with the liner oxide layer formed therein, wherein the second insulation layer has a lower etch rate than that of the first insulation layer.


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