The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 02, 2012
Filed:
Mar. 09, 2010
Da-wen Lin, Hsin-Chu, TW;
Che-min Chu, Xinzhuang, TW;
Tsung-hung LI, Hsin-Chu, TW;
Chih-hung Tseng, Zhutang Township, TW;
Yen-chun Lin, Hsin-Chu, TW;
Chung-cheng Wu, Chu-Bei, TW;
Da-Wen Lin, Hsin-Chu, TW;
Che-Min Chu, Xinzhuang, TW;
Tsung-Hung Li, Hsin-Chu, TW;
Chih-Hung Tseng, Zhutang Township, TW;
Yen-Chun Lin, Hsin-Chu, TW;
Chung-Cheng Wu, Chu-Bei, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A method of forming a semiconductor structure includes providing a substrate including a fin at a surface of the substrate, and forming a fin field-effect transistor (FinFET), which further includes forming a gate stack on the fin; forming a thin spacer on a sidewall of the gate stack; and epitaxially growing a epitaxy region starting from the fin. After the step of epitaxially growing the epitaxy region, a main spacer is formed on an outer edge of the thin spacer. After the step of forming the main spacer, a deep source/drain implantation is performed to form a deep source/drain region for the FinFET.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile