The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2012

Filed:

Jul. 16, 2010
Applicants:

Chun-chia Chen, Taichung County, TW;

Ying-hung Chou, Tainan County, TW;

Zen-jay Tsai, Tainan, TW;

Shih-chieh Hsu, Taipei County, TW;

Yi-chung Sheng, Tainan, TW;

Chi-horn Pai, Tainan County, TW;

Inventors:

Chun-Chia Chen, Taichung County, TW;

Ying-Hung Chou, Tainan County, TW;

Zen-Jay Tsai, Tainan, TW;

Shih-Chieh Hsu, Taipei County, TW;

Yi-Chung Sheng, Tainan, TW;

Chi-Horn Pai, Tainan County, TW;

Assignee:

United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a CMOS device includes providing a substrate having a first region and a second region; forming a first gate structure and a second gate structure, each of the gate structures comprising a sacrificial layer and a hard mask layer; forming a patterned first protecting layer covering the first region and a first spacer on sidewalls of the second gate structure; performing an etching process to form first recesses in the substrate; performing a SEG process to form epitaxial silicon layers in each first recess; forming a patterned second protecting layer covering the second region; and performing a dry etching process with the patterned second protecting layer serving as an etching mask to etch back the patterned first protecting layer to form a second spacer on sidewalls of the first gate structure and to thin down the hard mask layer on the first gate structure.


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