The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 25, 2012
Filed:
Aug. 07, 2009
Mark Robert Visokay, Wappingers Falls, NY (US);
Freidoon Mehrad, Plano, TX (US);
Richard L. Guldi, Dallas, TX (US);
Yaw Samuel Obeng, Frisco, TX (US);
Mark Robert Visokay, Wappingers Falls, NY (US);
Freidoon Mehrad, Plano, TX (US);
Richard L. Guldi, Dallas, TX (US);
Yaw Samuel Obeng, Frisco, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method of forming fully silicided (FUSI) gates in MOS transistors which is compatible with wet etch processes used in source/drain silicide formation is disclosed. The gate silicide formation step produces a top layer of metal rich silicide which is resistant to removal in wet etch processes. A blocking layer over active areas prevents source/drain silicide formation during gate silicide formation. Wet etches during removal of the blocking layer and source/drain metal strip do not remove the metal rich gate silicide layer. Anneal of the gate silicide to produce a FUSI gate with a desired stoichiometry is delayed until after formation of the source/drain silicide. The disclosed method is compatible with nickel and nickel-platinum silicide processes.