The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2012

Filed:

Mar. 24, 2009
Applicants:

Shih-yu Wang, Taipei, TW;

Chia-ling LU, Luzhou, TW;

Yan-yu Chen, Taipei, TW;

Yu-lien Liu, Hsinchu, TW;

Tao-cheng LU, Hsinchu, TW;

Inventors:

Shih-Yu Wang, Taipei, TW;

Chia-Ling Lu, Luzhou, TW;

Yan-Yu Chen, Taipei, TW;

Yu-Lien Liu, Hsinchu, TW;

Tao-Cheng Lu, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/74 (2006.01); H01L 23/62 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes a first well region of a first conductivity, a second well region of a second conductivity type, a source region of the second conductivity type within the first well region, and a drain region of the second conductivity type at least partially within the second well region. A well contact to the first well region is coupled to the source. A third doped region of the first conductivity type and a fourth doped region of the second conductivity type are located in the second well region. A first transistor includes the third doped region, the second well region, and the first well region. The first transistor is coupled to a switch device. A second transistor includes the second well region, the first well region, and the source region. The first and the second transistors are configured to provide a current path during an ESD event.


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