The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 28, 2012
Filed:
Apr. 22, 2011
Feng-yi Chang, Tainan, TW;
Yi-po Lin, Tainan, TW;
Jiunn-hsiung Liao, Tainan, TW;
Shang-yuan Tsai, Kaohsiung, TW;
Chih-wen Feng, Tainan, TW;
Shui-yen LU, Hsinchu County, TW;
Ching-pin Hsu, Tainan, TW;
Feng-Yi Chang, Tainan, TW;
Yi-Po Lin, Tainan, TW;
Jiunn-Hsiung Liao, Tainan, TW;
Shang-Yuan Tsai, Kaohsiung, TW;
Chih-Wen Feng, Tainan, TW;
Shui-Yen Lu, Hsinchu County, TW;
Ching-Pin Hsu, Tainan, TW;
United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
A method for fabricating MOS transistor includes the steps of: overlapping a second stress layer on an etching stop layer and a first stress layer at a boundary region of the substrate; forming a dielectric layer on the first stress layer and the second stress layer; performing a first etching process to partially remove the dielectric layer for exposing a portion of the second stress layer at the boundary region; performing a second etching process to partially remove the exposed portion of the second stress layer for exposing the etching stop layer; performing a third etching process to partially remove the exposed portion of the etching stop layer for exposing the first stress layer at the boundary region; and performing a fourth etching process partially remove the exposed portion of the first stress layer.