The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2012
Filed:
Aug. 20, 2010
Method of forming a vertical diode and method of manufacturing a semiconductor device using the same
Sang-jin Park, Gyeonggi-do, KR;
Kong-soo Lee, Gyeonggi-do, KR;
Yong-woo Hyung, Gyeonggi-do, KR;
Young-sub You, Gyeonggi-do, KR;
Jae-jong Han, Seoul, KR;
Sang-Jin Park, Gyeonggi-do, KR;
Kong-Soo Lee, Gyeonggi-do, KR;
Yong-Woo Hyung, Gyeonggi-do, KR;
Young-Sub You, Gyeonggi-do, KR;
Jae-Jong Han, Seoul, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.