The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2012

Filed:

Oct. 07, 2010
Applicants:

David M. Fried, Brewster, NY (US);

Jeffrey B. Johnson, Essex Junction, VT (US);

Kevin Mcstay, Hopewell Junction, NY (US);

Paul C. Parries, Wappingers Falls, NY (US);

Chengwen Pei, Danbury, CT (US);

Gan Wang, Fishkill, NY (US);

Geng Wang, Stormville, NY (US);

Yanli Zhang, San Jose, CA (US);

Inventors:

David M. Fried, Brewster, NY (US);

Jeffrey B. Johnson, Essex Junction, VT (US);

Kevin McStay, Hopewell Junction, NY (US);

Paul C. Parries, Wappingers Falls, NY (US);

Chengwen Pei, Danbury, CT (US);

Gan Wang, Fishkill, NY (US);

Geng Wang, Stormville, NY (US);

Yanli Zhang, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/84 (2006.01); H01L 21/338 (2006.01);
U.S. Cl.
CPC ...
Abstract

An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage.


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