The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 2012
Filed:
May. 12, 2010
Wen-chou Vincent Wang, Cupertino, CA (US);
Yuan LI, Sunnyvale, CA (US);
Bruce Euzent, Sunnyvale, CA (US);
Vadali Mahadev, San Jose, CA (US);
Wen-chou Vincent Wang, Cupertino, CA (US);
Yuan Li, Sunnyvale, CA (US);
Bruce Euzent, Sunnyvale, CA (US);
Vadali Mahadev, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Provided are semiconductor die flip chip packages and semiconductor die flip chip package components where certain properties of the packages/components are controlled to facilitate management of the package stresses. Also provided are fabrication methods for such packages and package components. For instance, the thickness of a die can be controlled such that the stress generated/experienced by the die is minimized. As such, the package stress is managed to suitable levels for incorporation of a low-K Si die and/or a thin package substrate. Further, a thin die can be attached to a heat spreader to increase the rigidity for easier handling during fabrication of the semiconductor die flip chip package.