The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 2012
Filed:
Apr. 09, 2010
Jie Diao, Fremont, CA (US);
Garlen C. Leung, San Jose, CA (US);
Christopher Heung-gyun Lee, San Jose, CA (US);
Lakshmanan Karuppiah, San Jose, CA (US);
Jie Diao, Fremont, CA (US);
Garlen C. Leung, San Jose, CA (US);
Christopher Heung-Gyun Lee, San Jose, CA (US);
Lakshmanan Karuppiah, San Jose, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
A method and apparatus for polishing or planarizing a pre-metal dielectric layer by a chemical mechanical polishing process are provided. The method comprises providing a semiconductor substrate having feature definitions formed thereon, forming a pre-metal dielectric layer over the substrate, wherein the as-deposited pre-metal dielectric layer has an uneven surface topography, and planarizing the uneven surface topography of the pre-metal dielectric layer using chemical mechanical polishing techniques, wherein planarizing the uneven surface topography comprises polishing the pre-metal dielectric layer with a fixed abrasive polishing pad and a first polishing composition to remove a bulk portion of the pre-metal dielectric layer and achieve a first predetermined planarity, and polishing the pre-metal dielectric layer with a non-abrasive polishing pad and high selectivity slurry to remove a residual portion of the pre-metal dielectric and achieve a second predetermined planarity.