The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 2012
Filed:
Sep. 03, 2009
Shan-chyun Ku, Hsinchu, TW;
Marcelo Glusman, San Jose, CA (US);
Yee-wing Hsieh, Pleasanton, CA (US);
Manish Pandey, Saratoga, CA (US);
Angela Krstic, San Diego, CA (US);
Sarath Kirihennedige, Fremont, CA (US);
Shan-Chyun Ku, Hsinchu, TW;
Marcelo Glusman, San Jose, CA (US);
Yee-Wing Hsieh, Pleasanton, CA (US);
Manish Pandey, Saratoga, CA (US);
Angela Krstic, San Diego, CA (US);
Sarath Kirihennedige, Fremont, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Certain embodiments of the present invention enable comparisons between constrained circuit designs by generating timing graphs for circuit designs, mapping timing constraints to the timing graphs, and comparing the mapped timing constraints from different timing graphs. Typically this comparison is made by identifying corresponding nodes in two or more timing graphs. Specific embodiments are also directed to multiple SDC (Synopsis Design Constraint) constraint specifications for a circuit and multiple constraint sets for different operational modes of a circuit.