The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 2012
Filed:
Oct. 05, 2010
Yuan-chih Hsieh, Hsinchu, TW;
Richard Chu, Taipei, TW;
Ming-tung Wu, Hsinchu, TW;
Martin Liu, Yonghe, TW;
Lan-lin Chao, Sindian, TW;
Chia-shiung Tsai, Hsin-Chu, TW;
Yuan-Chih Hsieh, Hsinchu, TW;
Richard Chu, Taipei, TW;
Ming-Tung Wu, Hsinchu, TW;
Martin Liu, Yonghe, TW;
Lan-Lin Chao, Sindian, TW;
Chia-Shiung Tsai, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A semiconductor device includes a substrate wafer, a dielectric layer overlying the substrate wafer, a patterned conductor layer in the dielectric layer, and a first barrier layer overlying the conductor layer. A silicon top wafer is bonded to the dielectric layer. A via is formed through the top wafer and a portion of the dielectric layer to the first barrier layer. A sidewall dielectric layer is formed along inner walls of the via, adjacent the top wafer to a distance below an upper surface of the top wafer, forming a sidewall dielectric layer shoulder. A sidewall barrier layer is formed inward of the sidewall dielectric layer, lining the via from the first barrier layer to the upper surface of the top wafer. A conductive layer fills the via and a top barrier layer is formed on the conductive layer, the sidewall barrier layer, and the top wafer.