The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2012

Filed:

Mar. 26, 2008
Applicants:

Christoph Ellmers, Dresden, DE;

Thomas Uhlig, Dresden, DE;

Felix Fuernhammer, Dresden, DE;

Michael Stoisiek, Erlangen, DE;

Michael Gross, Eckental, DE;

Inventors:

Christoph Ellmers, Dresden, DE;

Thomas Uhlig, Dresden, DE;

Felix Fuernhammer, Dresden, DE;

Michael Stoisiek, Erlangen, DE;

Michael Gross, Eckental, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods of forming, on a substrate, a first lateral high-voltage MOS transistor and a second lateral high-voltage MOS transistor complementary to said first one are disclosed. According to one embodiment, the method includes (1) providing a substrate of a first conductivity type including a first active region for said first lateral high-voltage MOS transistor and a second active region for said second lateral high-voltage MOS transistor and (2) forming at least one first doped region of the first conductivity type in the first active region and forming in the second active region a drain extension region of the second conductivity type extending from a substrate surface to an interior of the substrate, including a concurrent implantation of dopants through openings of one and the same mask into the first and second active regions. Forming of the at least one first doped region may be a sub step of a superior step of forming a double RESURF structure in the first lateral high-voltage MOS transistor, and forming the double RESURF structure may include forming doped RESURF regions as two first doped regions, one thereof above and one thereof below the drift region of the first lateral high-voltage MOS transistor, and as two further doped regions, one thereof above and one thereof below the drain extension regions of the second lateral high-voltage MOS transistor, wherein the first doped RESURF regions have an inverse conductivity type with respect to the drift region and the further doped regions have inverse conductivity type as compared to the drain extension region.


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