The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2012
Filed:
Sep. 08, 2010
Po-hung Chen, Taipei, TW;
Chin-huang Wang, Pingjhen, TW;
Yen-chieh Huang, Zhubei, TW;
Sung-chieh Lin, Zhubei, TW;
Kuoyuan (Peter) Hsu, San Jose, CA (US);
Po-Hung Chen, Taipei, TW;
Chin-Huang Wang, Pingjhen, TW;
Yen-Chieh Huang, Zhubei, TW;
Sung-Chieh Lin, Zhubei, TW;
Kuoyuan (Peter) Hsu, San Jose, CA (US);
Abstract
Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile