The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2012

Filed:

Aug. 06, 2009
Applicants:

Jun-beom Park, Seoul, KR;

Soon-moon Jung, Gyeonggi-do, KR;

Han-soo Kim, Gyeonggi-do, KR;

Jae-hoon Jang, Gyeonggi-do, KR;

Jae-hun Jeong, Gyeonggi-do, KR;

Jong-in Yun, Seoul, KR;

Mi-so Hwang, Seoul, KR;

Inventors:

Jun-Beom Park, Seoul, KR;

Soon-Moon Jung, Gyeonggi-do, KR;

Han-Soo Kim, Gyeonggi-do, KR;

Jae-Hoon Jang, Gyeonggi-do, KR;

Jae-Hun Jeong, Gyeonggi-do, KR;

Jong-In Yun, Seoul, KR;

Mi-So Hwang, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

A stack-type semiconductor device and a method of manufacturing the same are provided. The stack-type semiconductor device includes an insulation layer on a single-crystalline substrate, a contact plug penetrating the insulation layer to contact the single-crystalline substrate, an upper semiconductor pattern including an impurity region and a gate structure positioned between the impurity regions on the upper semiconductor pattern. An upper surface of the contact plug contacts a lower surface of the semiconductor pattern. An operation failure of the stack-type semiconductor device is reduced since the upper semiconductor pattern is electrically connected to the single-crystalline semiconductor substrate.


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