The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 22, 2012
Filed:
Apr. 15, 2011
Takashi Ishigaki, Hino, JP;
Ryuta Tsuchiya, Tokyo, JP;
Yusuke Morita, Amagasaki, JP;
Nobuyuki Sugii, Tokyo, JP;
Shinichiro Kimura, Kunitachi, JP;
Toshiaki Iwamatsu, Toyonaka, JP;
Takashi Ishigaki, Hino, JP;
Ryuta Tsuchiya, Tokyo, JP;
Yusuke Morita, Amagasaki, JP;
Nobuyuki Sugii, Tokyo, JP;
Shinichiro Kimura, Kunitachi, JP;
Toshiaki Iwamatsu, Toyonaka, JP;
Renesas Electronics Corporation, Kanagawa, JP;
Abstract
There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. The first elevated layer is thicker than the second elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.