The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2012
Filed:
Jan. 15, 2008
Robert D. Herzl, South Burlington, VT (US);
Robert S. Horton, Colchester, VT (US);
Kenneth A. Lauricella, Colchester, VT (US);
David W. Milton, Underhill, VT (US);
Clarence R. Ogilvie, Huntington, VT (US);
Paul M. Schanely, Essex Junction, VT (US);
Nitin Sharma, South Burlington, VT (US);
Tad J. Wilder, South Hero, VT (US);
Charles B. Winn, Colchester, VT (US);
Robert D. Herzl, South Burlington, VT (US);
Robert S. Horton, Colchester, VT (US);
Kenneth A. Lauricella, Colchester, VT (US);
David W. Milton, Underhill, VT (US);
Clarence R. Ogilvie, Huntington, VT (US);
Paul M. Schanely, Essex Junction, VT (US);
Nitin Sharma, South Burlington, VT (US);
Tad J. Wilder, South Hero, VT (US);
Charles B. Winn, Colchester, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A chip design methodology. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB).