The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2012
Filed:
Aug. 27, 2009
Vikram Iyengar, Pittsburgh, PA (US);
Pamela S. Gillis, Essex Junction, VT (US);
David E. Lackey, Essex Junction, VT (US);
Steven F. Oakland, Essex Junction, VT (US);
Vikram Iyengar, Pittsburgh, PA (US);
Pamela S. Gillis, Essex Junction, VT (US);
David E. Lackey, Essex Junction, VT (US);
Steven F. Oakland, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of hold fault modeling and test generation. The method includes first modeling a fast-to-rise and a fast-to-fall hold fault for a plurality of circuit nets. Testing a fast-to-rise hold fault is accomplished by: setting up a logic value on each of the plurality of circuit nodes to 0; transitioning each of the plurality of circuit nodes from 0 to 1 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 0 to 1. Testing a fast-to-fall hold is accomplished by: setting up a logic value on each of the plurality circuit nodes to 1; transitioning each of the plurality of circuit nodes from 1 to 0 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 1 to 0.