The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2012
Filed:
Jan. 20, 2012
Fujio Masuoka, Tokyo, JP;
Tomohiko Kudo, Tokyo, JP;
Shintaro Arai, Tokyo, JP;
Hiroki Nakamura, Tokyo, JP;
Fujio Masuoka, Tokyo, JP;
Tomohiko Kudo, Tokyo, JP;
Shintaro Arai, Tokyo, JP;
Hiroki Nakamura, Tokyo, JP;
Unisantis Electronics Singapore Pte Ltd., Peninsula Plaza, SG;
Abstract
An SGT production method includes forming a pillar-shaped first-conductive-type semiconductor layer and forming a second-conductive-type semiconductor layer underneath the first-conductive-type semiconductor layer. A dummy gate dielectric film and a dummy gate electrode are formed around the first-conductive-type semiconductor layer and a first dielectric film is formed on an upper region of a sidewall of the first-conductive-type semiconductor layer in contact with a top of the gate electrode. A first dielectric film is formed on a sidewall of the gate electrode and a second-conductive-type semiconductor layer is formed in an upper portion of the first-conductive-type semiconductor layer. A second-conductive-type semiconductor layer is formed in an upper portion of the first-conductive-type semiconductor layer and a metal-semiconductor compound is formed on each of the second-conductive-type semiconductor layers. The dummy gate dielectric film and the dummy gate electrode are removed and a high-k gate dielectric film and a metal gate electrode are formed.