Reducing effects of parasitic transistors in thyristor-based memory using local thinning or implanting

Abstract

Method and apparatus for an integrated circuit having memory including thyristor-based memory cells is described. A pair of the thyristor-based memory cells are commonly coupled via a bitline region, where a parasitic bipolar junction transistor is defined therebetween responsive to the bitline region being common. In another implementation, the pair of the thyristor-based memory cells are commonly coupled via the anode region, where a parasitic bipolar junction transistor is defined therebetween responsive to the anode region being common. The common bitline or anode region, respectively, has a locally thinned region to inhibit charge transfer between the pair via the parasitic bipolar junction transistor. Moreover, a method for forming a field-effect transistor on a silicon-on-insulator wafer is described, where charge transfer facilitated by a parasitic bipolar transistor is reduced responsive to an increase in dopants at least proximate to an insulator layer.