The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 01, 2012
Filed:
Apr. 27, 2009
Jared Levan Zerbe, Woodside, CA (US);
Kevin S. Donnelly, Los Altos, CA (US);
Stefanos Sidiropoulos, Palo Alto, CA (US);
Donald C. Stark, Los Altos Hills, CA (US);
Mark A. Horowitz, Menlo Park, CA (US);
Leung Yu, Los Altos, CA (US);
Roxanne VU, San Jose, CA (US);
Jun Kim, Redwood City, CA (US);
Bruno W. Garlepp, Sunnyvale, CA (US);
Tsyr-chyang Ho, San Jose, CA (US);
Benedict Chung-kwong Lau, San Jose, CA (US);
Jared LeVan Zerbe, Woodside, CA (US);
Kevin S. Donnelly, Los Altos, CA (US);
Stefanos Sidiropoulos, Palo Alto, CA (US);
Donald C. Stark, Los Altos Hills, CA (US);
Mark A. Horowitz, Menlo Park, CA (US);
Leung Yu, Los Altos, CA (US);
Roxanne Vu, San Jose, CA (US);
Jun Kim, Redwood City, CA (US);
Bruno W. Garlepp, Sunnyvale, CA (US);
Tsyr-Chyang Ho, San Jose, CA (US);
Benedict Chung-Kwong Lau, San Jose, CA (US);
Rambus Inc., Sunnyvale, CA (US);
Abstract
A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.