The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2012

Filed:

Dec. 22, 2009
Applicants:

James E. Kohl, Reading, MA (US);

Charles W. Eichelberger, Wakefield, MA (US);

Inventors:

James E. Kohl, Reading, MA (US);

Charles W. Eichelberger, Wakefield, MA (US);

Assignee:

EPIC Technologies, Inc., Woburn, MA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/30 (2006.01);
U.S. Cl.
CPC ...
Abstract

Stackable circuit structures and methods of fabrication are provided employing first level metallization directly on a chips-first layer(s), which includes: a chip(s), each with a pad mask over its upper surface and openings exposing its contact pads; electrically conductive structures; and structural dielectric material surrounding the side surfaces of the chips and the conductive structures. Each chips-first layer further includes a metallization layer on the front surface of the layer, residing at least partially on the pad mask and extending over an edge of the chip. Together, the pad mask and the structural material electrically isolate the metallization layer from the chip. Input/output interconnect structures physically and electrically contact the metallization layer over the front surface and/or the lower surfaces of the electrically conductive structures at the back surface of the chips-first layer, to facilitate input/output connection to chips of the layers in a stack.


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