The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2012
Filed:
Jun. 06, 2008
Sanford Chu, Singapore, SG;
Yisuo LI, Singapore, SG;
Guowei Zhang, Singapore, SG;
Verma Purakh, Singapore, SG;
Sanford Chu, Singapore, SG;
Yisuo Li, Singapore, SG;
Guowei Zhang, Singapore, SG;
Verma Purakh, Singapore, SG;
Globalfoundries Singapore Pte. Ltd., Woodlands, SG;
Abstract
An LDMOS device includes a substrate having a surface and a gate electrode overlying the surface and defining a channel region in the substrate below the gate electrode. A drain region is spaced apart from the channel region by an isolation region. The isolation region includes a region of high tensile stress and is configured to induce localized stress in the substrate in close proximity to the drain region. The region of high tensile stress in the isolation region can be formed by high-stress silicon oxide or high-stress silicon nitride. In a preferred embodiment, the isolation region is a shallow trench isolation region formed in the substrate intermediate to the gate electrode and the drain region.