The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2012
Filed:
Sep. 01, 2010
Ru-shang Hsiao, Jhubei, TW;
Min Cao, Hsin-Chu, TW;
Chung-te Lin, Tainan, TW;
Ta-ming Kuan, Zhongli, TW;
Cheng-tung Hsu, Yun-Ling Hsien, TW;
Ru-Shang Hsiao, Jhubei, TW;
Min Cao, Hsin-Chu, TW;
Chung-Te Lin, Tainan, TW;
Ta-Ming Kuan, Zhongli, TW;
Cheng-Tung Hsu, Yun-Ling Hsien, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.