The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 27, 2012
Filed:
Jan. 30, 2009
Qiushi Chen, San Jose, CA (US);
Beifang Qiu, Sunnyvale, CA (US);
Charles C. Chiang, Saratoga, CA (US);
Xiaoping HU, Sunnyvale, CA (US);
Mathew Koshy, San Mateo, CA (US);
Baribrata Biswas, San Jose, CA (US);
Qiushi Chen, San Jose, CA (US);
Beifang Qiu, Sunnyvale, CA (US);
Charles C. Chiang, Saratoga, CA (US);
Xiaoping Hu, Sunnyvale, CA (US);
Mathew Koshy, San Mateo, CA (US);
Baribrata Biswas, San Jose, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
One embodiment of the present invention provides a system that performs an RLC extraction for a three-dimensional integrated circuit (3D-IC) die. During operation, the system receives a 3D-IC die description. The system then transforms the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description. Next, for each 2D-IC die description in the set of 2D-IC die descriptions, the system performs an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file. The system then combines the set of 2D-IC RLC netlist files for the set of 2D-IC die descriptions to form an RLC netlist file for the 3D-IC die description.