The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 20, 2012

Filed:

Jun. 19, 2009
Applicants:

Yemin Dong, Singapore, SG;

Purakh Raj Verma, Singapore, SG;

Xin Zou, Singapore, SG;

Chao Cheng, Singapore, SG;

Shao-fu Sanford Chu, Singapore, SG;

Inventors:

Yemin Dong, Singapore, SG;

Purakh Raj Verma, Singapore, SG;

Xin Zou, Singapore, SG;

Chao Cheng, Singapore, SG;

Shao-fu Sanford Chu, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/94 (2006.01); H01L 29/76 (2006.01); H01L 31/119 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate having an active region, implanted with impurities of a first type at a first concentration; forming an isolation region around the active region; forming a parasitic transistor by applying a gate electrode, implanted with impurities of a second type at a second concentration, over the active region and the isolation region; and applying an isolation edge implant, with the impurities of the first type at a third concentration greater than or equal to the second concentration, for suppressing the parasitic transistor.


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