The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 20, 2012

Filed:

May. 19, 2008
Applicants:

Mahalingam Nandakumar, Richardson, TX (US);

Said Ghneim, Dallas, TX (US);

Frank Scott Johnson, Wappingers Falls, NY (US);

Inventors:

Mahalingam Nandakumar, Richardson, TX (US);

Said Ghneim, Dallas, TX (US);

Frank Scott Johnson, Wappingers Falls, NY (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of forming sidewall spacers for a gate in a semiconductor device includes depositing a gate oxide layer over a gate and source/drain regions, and using a thermal anneal to oxidize silicon of the substrate and silicon of the gate after formation of the deposited oxide layer. A sidewall layer is deposited over the oxide layer following the oxidation, and the sidewall layer and oxide layer are patterned to form the sidewall spacers.


Find Patent Forward Citations

Nandakumar, Mahalingam. (2012). Method of forming sidewall spacers to reduce formation of recesses in the substrate and increase dopant retention in a semiconductor device (U.S. Patent No. 8138045). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8138045

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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