The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 13, 2012

Filed:

Feb. 15, 2011
Applicants:

Lu-ping Chiang, Hsinchu, TW;

Hsiu-han Liao, Hsinchu, TW;

Inventors:

Lu-Ping Chiang, Hsinchu, TW;

Hsiu-Han Liao, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/338 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating a memory is provided. A substrate including a memory region and a periphery region is provided. A plurality of gates each having spacers is formed on the substrate. A plurality of openings is formed between the gates in the memory region. A first material layer is formed in the memory region to cover the gates and fill the openings. A barrier layer is formed on the substrate to cover the gates in the periphery region and the first material layer in the memory region. A second material layer is formed on the substrate in the periphery region to cover the barrier layer in the periphery region. The barrier layer covering the first material layer is removed. The first material layer is partially removed to form a plurality of second openings. Each second opening is disposed on a top of the gate in the memory region.


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