The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 06, 2012
Filed:
Apr. 11, 2007
Deepak D. Sherlekar, Cupertino, CA (US);
Gene Sluss, Cupertino, CA (US);
Tushar Gheewala, Los Altos, CA (US);
Deepak D. Sherlekar, Cupertino, CA (US);
Gene Sluss, Cupertino, CA (US);
Tushar Gheewala, Los Altos, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
Various methods and apparatuses are described in which an integrated circuit is organized into rows and columns of macro cells having a layout architecture that includes at least two metal layers and a plurality of traces carrying three or more different potentials of voltage routed by the metal layers. A first, a second, and a third adjacent metal layers extend across the integrated circuit. The plurality of traces carry three or more different potentials of voltage and are routed in the metal layers. A first power trace supplies a VDD voltage potential. A second power trace supplies a VSS voltage potential. A third power trace supplies a third voltage potential to support sleep modes and retain data during sleep modes. All three power supply traces connect to one or more transistors in a first macro cell.