The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2012
Filed:
Mar. 12, 2010
Dong-kil Shin, Hwaseong-si, KR;
Shle-ge Lee, Seoul, KR;
Jong-joo Lee, Gyeonggi-do, KR;
Jong-ho Lee, Hwaseong-si, KR;
Dong-Kil Shin, Hwaseong-si, KR;
Shle-Ge Lee, Seoul, KR;
Jong-Joo Lee, Gyeonggi-do, KR;
Jong-Ho Lee, Hwaseong-si, KR;
Samsung Electronics Co., Ltd., Suwon-Si, KR;
Abstract
In one embodiment, a semiconductor device includes a semiconductor substrate and a bonding pad disposed thereon. The semiconductor device also includes a passivation layer, a buffer layer, and an insulating layer sequentially stacked on the semiconductor substrate. According to one aspect, a first recess is defined within the passivation layer, the buffer layer, and the insulating layer to expose at least a region of the bonding pad and a second recess is defined within the insulating layer to expose at least a region of the buffer layer and spaced apart from the first recess such that a portion of the insulating layer is interposed therebetween. Further, the semiconductor device includes a conductive solder bump disposed within the first and second recesses. The conductive solder bump may be connected to the bonding pad in the first recess and supported by the buffer layer through a protrusion of the conductive solder bump extending into the second recess.