The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2012
Filed:
Nov. 13, 2008
Sun-won Kang, Seoul, KR;
Young-hee Song, Seongnam-si, KR;
Tae-gyeong Chung, Suwon-si, KR;
Nam-seog Kim, Yongin-si, KR;
Seung-duk Baek, Hwaseong-si, KR;
Sun-Won Kang, Seoul, KR;
Young-Hee Song, Seongnam-si, KR;
Tae-Gyeong Chung, Suwon-si, KR;
Nam-Seog Kim, Yongin-si, KR;
Seung-Duk Baek, Hwaseong-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.